The last few years have witnessed tremendous advancements in the field of integrated circuit technology. In its infancy, integrated circuit technology permitted fabrication of several discreet transistor elements on a single wafer of silicon material. In recent years, though, improvements in fabrication technology have permitted integrated circuits to become so dense that a single chip may contain thousands of transistor cell elements. An important feature of large-scale integrated circuits is the circuit "architecture" which is the organized structure of the circuit elements. The present invention relates to an improved architecture for configurable large scale and very large-scale integrated circuits.
Integrated circuit technology is broadly divided into two fields, the standard circuit field and the custom circuit field. In the field of standard circuits, a consumer merely purchases a pre-designed integrated circuit that is already "wired" to perform a selected function. In the field of custom circuits, the consumer determines his own logic designs and the fabricator implements that logic design as a circuit formed of logic elements formed generally on a silicon wafer according to the fabrication technique utilized by the particular fabricator. The field of custom integrated circuits includes both fully-customized circuits and semi-customized circuits. For semi-custom circuits, the consumer provides the fabricator with a logic description corresponding to his circuit requirements that enables the fabricator to determine a "wiring pattern." The fabricator then takes a chip organized with the fabricator's architecture and interconnects the elements in that architecture to form the customized circuit. While the present invention is particularly adaptable for use in semi-custom applications, the present chip architecture is completely suitable for standard circuits as well.
Chip fabricators employ three common approaches in the field of semi-custom circuit design. In a first one of these approaches, fabricators employ gate arrays that are organized in a uniform manner so that the customer merely supplies his logic requirements, and the fabricator determines the interconnect data. In the gate array technique, columns of cell elements are fabricated on a substrate with each of these cell elements comprising an unconnected plurality of both n channel and p channel transistor elements. Interconnects are then made among the transistor elements in each cell and among the cell elements to each other so that the gate array is "wired" to perform a desired logic function. Areas between the columns of cell elements provide routing or "wiring" channels to allow the interconnects between cell elements to be made.
A second technique commonly used employs standard cells which may be fabricated on a substrate. Here, the customer selects among standard cell elements, for example, AND gates, OR gates, NAND gates, and NOR gates which are already interconnected; these standard cell elements are internally preprogrammed with their own interconnects. Once the user selects the desired cells and provides the cell-to-cell interconnect data, the fabricator then fabricates the desired standard cells on the substrate and wires the standard cells together to provide the desired logic circuit. These standard cells are also commonly organized as columns of cell elements on the substrate material.
The third technique utilized in the field of semicustom chip fabrication is referred to as programmable logic arrays or PLA technology. While in some respects the PLA chip organization is the closest of the three techniques to the present invention, the chip architecture for a PLA is quite different from that described in the present invention. In PLA architecture, a first matrix of transistor elements defines a field of AND terms and a second, continguous matrix of transistors defines a field of OR terms. Rows of transistors in the AND field may be interconnected to columns of transistors in the OR field by interconnects, such as metal strips, extending completely across the two contiguous fields. Linear input interconnects extend across the rows of the AND field and continue across the columns of the OR field with these interconnects providing inputs to the PLA. Linear output interconnects also extend across the rows of transistors in the OR field perpendicular to the input interconnects and provide outputs for the PLA. A strip of nonconfigurable logic structures, such as flip flop elements, is provided adjacent the OR field so that the output interconnects extend across the logic structures as well. In PLA technology, the gates of each transistor element may be selectively interconnected to its respective input interconnect or output interconnect, and the output interconnects may be connected, where desired, to the logic structures so that the logic array performs a desired logic function.
While PLA devices perhaps provide the most straightforward approach to forming large-scale and very large-scale integrated circuits, there is a very undesireable consequence of this approach when more and more transistors are desired to be incorporated into the logic array. Specifically, as the number of gates or transistors increases, the chip size grows enormously. More particularly, during fabrication a number of individual chips are fabricated simultaneously on a larger, usually disk-shaped wafer. The individual chips are then cut apart of "diced" from one another for subsequent packaging. In the fabrication process, though, defects randomly occur across the silicon wafer. Since a defect occurring in a given chip typically ruins that chip, only those chips having virtually no defects are useable. As the size of the individual chip grows to accommodate more and more transistor elements, fewer chips may be diced from a given size wafer and the chances that a single chip will contain one of the wafer's defects increases exponentially. Accordingly, as the power of the logic array increases, its cost is greatly increased due to the lower dice yield that is achieved. This dimension problem is also true for standard cells and gate arrays.
Accordingly, there is a need for an improved chip architecture that permits higher gate count devices yet which allows the physical dimensions of the chip to remain smaller. It is further desireable to have an improved architecture that provides both the advantages of low circuit development costs resulting from the use of a predefined chip architecture and lower device costs resulting from the smaller chip size.